1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to field effect devices fabricated in silicon-on-insulator (SOI) structure.
2. Description of the Related Art
Silicon-on-insulator (SOI) technology employs a layer of semiconductor material overlying an insulator layer on a supporting bulk wafer. Fully depleted SOI metal oxide semiconductor (MOS) transistors are attractive candidates for use in very large scale integrated (VLSI) circuits, due to numerous advantages over bulk silicon and thick-film (partially depleted) SOI devices. The reported improvements include reduced short-channel effects, improved subthreshold slope, and higher transconductance.
However, these SOI MOS transistors suffer from several problems. One problem is floating body effects in channel of the field effect transistor. This deficiency is the main barrier to building high density, high speed SOI circuits using submicron MOS devices.
Another significant problem in thin SOI device design is lowering the breakdown voltage compared to bulk transistors. The early breakdown is a result of the feedback between the hole current and the parasitic lateral bipolar transistor. The breakdown voltage becomes very sensitive to variations in the silicon film thickness, that is, the breakdown voltage decreases as the film thickness is decreased. Additionally, the reduction of the silicon film thickness in SOI MOS transistor gives rise to high source/drain series resistance, which in turn lowers the device operation speed.
In an effort to avoid aforementioned problems, numerous researches have been reported. Problems due to the floating body effect and the low breakdown voltage can be solved by providing a contact to the body for hole current collection. However, the currently available hole collection schemes is very inefficient and consume significant amounts of device area. Also, a dual source structure using the implantation of germanium into the SOI device channel to suppress parasitic bipolar effects has been proposed, which is sensitive to process variations.
One solution to the source/drain series resistance problem is to selectively reduce the silicon film thickness over the channel region. However, the resulting recessed region and the polysilicon gate are not automatically aligned. To allow for the possible misalignment, the recessed thin silicon region must be made longer than the gate. This reduces the device performance and density, and results in asymmetrical devices. Silicidation can help improve the series resistance, but it will create mechanical stress and the process is hard to control on thin film silicon.
Ultimately, the conventional SOI MOS technologies are disadvantageous in that high breakdown voltage cannot coexist with low source/drain resistance.